Most DDR3 designs do not move to DDR4 because the memory is too slow. They move because the board ran out of something else: a power budget, a square centimetre of PCB, or a supply horizon shorter than the product's service life. Getting the order of those reasons right separates a migration that pays for itself from one that adds cost and risk for a number nobody uses.

DDR3 outlives its datasheet

DDR3 was specified for a market that has largely moved on, yet it still ships in volume, and not out of nostalgia. A DDR3 controller sits inside a large installed base of cost-sensitive SoCs, and the memory stays cheap per gigabyte because the fabs are long depreciated. For a product needing under roughly 3 GB/s with a service life ending before 2030, DDR3 is rational, not a compromise.

The pressure is supply-side: density stops scaling, temperature grades narrow to commercial, and lead times grow less predictable as fewer lines run the part.

The bandwidth arithmetic, done properly

Bandwidth is the number teams quote and the one they most often get wrong. The formula is narrow: data rate multiplied by bus width, divided by eight.

A single x16 DDR3-1600 channel gives 1600 × 16 ÷ 8, or 3.2 GB/s. A single x16 DDR4-2666 channel gives 5.3 GB/s. A single x16 LPDDR4X-4266 channel gives 8.5 GB/s. Those numbers are per channel. Most embedded SoCs run one or two channels, and a 32-bit DDR4 interface is two x16 devices in parallel, not one wider device.

Two corrections matter more than the headline rate. First, efficiency: a real controller reaches 65 to 80 percent of peak on mixed traffic, less on random access with frequent bank conflicts. Second, and more often missed, the number that limits a design is usually not average bandwidth but latency under load. A video pipeline that misses a frame deadline fails at 40 percent average utilisation if the access pattern is bursty.

So the useful question is not "how much faster is DDR4". It is "what is my worst-case latency requirement, and does the current interface have margin at the temperature and load the product actually runs at".

They are not competitors on the same board

DDR4 and LPDDR4X solve different problems and rarely appear as alternatives on one schematic.

DDR4 is a point-to-point or DIMM-oriented standard with a 1.2 V supply, a 64-bit natural width on DIMMs, and a strong ecosystem of industrial and x86-adjacent platforms. It is the natural path when the SoC has a DDR4 controller, when memory may need to be socketed or field-replaceable, and when the product is a box rather than a module.

LPDDR4X is a mobile-derived standard with a 0.6 V I/O supply, narrower channels, and a package-on-package or board-mounted topology built for tight boards and low power. It is the natural path when the device is sealed, fanless, battery-backed, or thin enough that a DIMM is physically impossible.

The constraint is the SoC: a processor supports one memory type, occasionally two in different speed bins. You do not choose between DDR4 and LPDDR4X; you choose a processor. Any comparison starting with the memory starts in the wrong place.

Power is the real argument for LPDDR4X

For a mains-powered industrial box, the difference between 1.2 V and 0.6 V I/O is a line item. For a sealed, fanless device, it can be the whole design.

LPDDR4X cuts I/O power roughly in proportion to the square of the voltage ratio, before considering the lower capacitance of a short, point-to-point topology. In a device with no fan, that saving converts directly into a lower case temperature, which converts into longer component life and a wider ambient specification. Thermal margin is often the real product differentiator, and memory I/O is one of the few places where it can be bought cheaply.

DDR4's counter-argument is practicality: sockets, industrial temperature grades and a wider density range. On a fan-cooled box the power case weakens.

What the migration actually costs

Teams underestimate the migration because they budget for the memory part and not for everything attached to it.

The SoC changes, or the board does. DDR3 to DDR4 usually means a new processor, hence new boot code, pin muxing and errata. LPDDR4X means a new stackup too, because routing and reference-plane rules tighten.

Power delivery grows. DDR4 needs 1.2 V with a tracking termination rail; LPDDR4X needs 1.1 V core and 0.6 V I/O with different sequencing. Each rail is a regulator and a layout constraint.

Layer count usually rises. A four-layer DDR3 board often becomes six layers for DDR4 and six to eight for LPDDR4X, depending on channel count and length matching tolerance. That is a per-unit cost that never appears in the memory price comparison.

Qualification restarts. New memory means new signal integrity work, new temperature margin testing, and in regulated products a new submission — the line item most often omitted.

Against that, the savings are real but slow: supply horizon, density roadmap, LPDDR4X power. Payback runs two to three generations, not one.

Three triggers that justify the move

Bandwidth or latency has become the binding constraint. Not "we could use more", but a measured failure: dropped frames, missed control-loop deadlines, a queue that overflows under peak load. Instrument first. If average utilisation is under 50 percent and latency is fine, bandwidth is not the reason.

The supply horizon is shorter than the product's service life. If the industrial customer expects ten years and the remaining DDR3 supply covers four, the migration is not optional, only the timing is. This is the most common real trigger, and the one most often discovered too late.

Thermal or mechanical limits are blocking the product. A fanless enclosure that cannot dissipate the DDR3 power, or a board that cannot fit the routing, has a physical problem that no amount of sourcing work solves.

If none applies, staying on DDR3 and spending the budget on a second source returns more. A migration for its own sake consumes a quarter of engineering capacity for a specification the product never needed.

Where the decision lands

Work it in this order: confirm what the SoC supports, measure whether bandwidth or latency is actually binding, check the supply horizon against the service life, then cost the rails, layers and requalification.

DDR4 fits socketed industrial boxes, x86-adjacent platforms and products needing replaceable memory. LPDDR4X fits sealed, fanless, thin or battery-backed devices. DDR3 stays correct for cost-driven products whose service life ends before the supply does.

The mistake is treating the memory generation as a quality marker. DDR3 with margin and a qualified second source beats LPDDR4X chosen for a roadmap slide.

If you are mapping a platform transition, we can work through the memory options against your SoC roadmap, thermal budget and expected service life. We supply DDR3, DDR4 and LPDDR4X families and have supported industrial customers through these transitions, so the discussion tends to be about constraints rather than part numbers.