An Ethernet PHY looks like a commodity part. It has a standard interface on one side and a transformer on the other, the datasheet is forty pages, and the price difference between two candidates is usually cents. That framing is why so many first-generation ports work on the bench and fail EMC, or link at gigabit on one board and negotiate down to 100 Mbps on the next.

The part is commodity. The channel around it is not.

Interface choice comes before part choice

Three interfaces cover most embedded designs, and they are not interchangeable.

RGMII carries gigabit over twelve signals: a 125 MHz clock, four data lines per direction, and control lines, with data sampled on both clock edges. It is cheap in silicon, needs no SerDes, and is the default on most cost-focused SoCs. Its weakness is timing. The clock and data skew budget is a couple of nanoseconds, and the PHY and the MAC each have an internal delay option that must be enabled on exactly one side. Enable both, or neither, and the link may work at room temperature and fail when the board warms up.

RMII halves the pin count by doubling the clock to 50 MHz, and is only good for 10/100. It is still the right choice for a control port that will never carry more than telemetry.

SGMII serialises the link at 1.25 Gbps per direction over a differential pair, with the clock embedded. It needs a SerDes on the SoC and a reference clock, but it routes over much longer distances and removes the RGMII skew problem entirely. On a board where the PHY sits at the far edge next to the connector and the SoC is in the middle, SGMII is usually the only comfortable option.

Above 1G the picture changes again: 2.5G and 10G ports use USXGMII, XFI or SGMII+ depending on the PHY family, and the reference clock jitter requirement becomes a specification you have to check rather than assume.

The magnetics budget

The transformer and its termination network are where projects lose EMC without noticing.

An integrated magnetics connector puts the transformer, common mode chokes and often the LEDs inside the RJ45. It saves board area and simplifies the layout, costs more per port, and constrains you to the connector vendor's electrical characteristics. Discrete magnetics cost less, give you control over the common mode choke and the centre tap termination, and take roughly twice the board area.

Either way, three things have to be designed rather than copied.

Centre tap termination. The PHY datasheet specifies how the centre taps are terminated — to a supply, to ground through a capacitor, or through a resistor network. Copying a reference design with a different PHY family is the single most common cause of a port that links but fails conducted emissions.

Common mode choke placement. It belongs between the PHY and the connector, close to the connector, with the differential pairs kept short and symmetric through it. A choke placed for layout convenience does less than the datasheet implies.

The unused pairs. On a 10/100 design, the two unused pairs still need termination to control common mode currents. Leaving them floating is a classic emissions failure at 30 to 100 MHz.

Add the Bob Smith termination on the cable side, and the chassis ground strategy, and this is a block that deserves its own schematic review page rather than a corner of the connector sheet.

Clock architecture decides more than it should

A 1G PHY typically needs a 25 MHz reference, either from a crystal or from the SoC's clock output. Three decisions follow.

Who sources the clock. If the PHY generates it and feeds the SoC, the PHY must start before the MAC is configured. If the SoC generates it, the PHY is a slave and the boot sequence is simpler. Mixing the two across a product family creates firmware variants nobody wants to maintain.

Crystal or oscillator. A crystal is cheaper and needs load capacitors matched to the PHY's specified value; an oscillator is more expensive and removes a tuning variable. On wide-temperature industrial designs, the crystal's frequency drift over temperature is a specification to check, not a detail.

Jitter, once you go above 1G. For 2.5G and 10G, the reference clock phase noise becomes part of the link budget. A clock that is fine for a 1G port may be marginal at 2.5G, and the failure mode is a link that trains slowly or drops under load.

Strapping pins, the silent failure

PHY configuration at power-up comes from strapping pins, which are usually shared with LED outputs or configuration signals. Their state is latched in the first milliseconds after reset.

Two consequences. First, anything driving those nets — an LED, a test point with a pull-up, a connector pin — can change the PHY's address, interface mode or clock direction at boot. Second, the latch happens before the SoC's GPIOs are configured, so software cannot fix a wrong strap. This is a hardware review item, and it produces failures that look like firmware bugs: a PHY that responds at the wrong MDIO address on some boards, or a port that comes up in the wrong mode after a warm reset.

A selection sequence

Define the port count and speed first, then the interface the SoC supports, then the distance from SoC to connector. That last number decides RGMII versus SGMII more often than any datasheet comparison.

Then check the magnetics against the PHY's specified termination, not against a reference design from another vendor. Confirm the clock source and who is the slave. Put the strapping pins on a review checklist with their required boot states. Check the thermal figure — a 1G PHY dissipates one to two watts, a 10G part several times that, and in a sealed industrial box that is a real constraint on where the PHY can sit.

Finally, test the port the way it will be used: long cable, worst-case temperature, EMC chamber. A port that links at the bench with a one-metre patch cable has demonstrated almost nothing.

If you are laying out a network port for an industrial or consumer product, we can review the PHY, magnetics and interface choices against your SoC and EMC targets. We supply Ethernet and interface parts and have supported designs through compliance testing, so the conversation tends to be about the channel rather than the catalogue.